1 ltc1477/LTC1478 the ltc ? 1477/LTC1478 protected high side switches provide extremely low r ds(on) switching with built-in protection against short-circuit and thermal overload con- ditions. a built-in charge pump generates gate drive higher than the supply voltage to fully enhance the internal nmos switch. this switch has no parasitic body diode and therefore no current flows through the switch when it is turned off and the output is forced above the input supply voltage. (dmos switches have parasitic body diodes that become forward biased under these conditions.) two levels of protection are provided by the ltc1477/LTC1478. the first level of protection is short- circuit current limit which is set at 2a. the short-circuit current can be reduced to as low as 0.85a by disconnect- ing portions of the power device (see applications infor- mation). the second level of protection is provided by thermal overload protection which limits the die tempera- ture to approximately 130 c. the ltc1477 single is available in 8-lead so packaging. the LTC1478 dual is available in 16-lead so packaging. single and dual protected high side switches features descriptio n u n extremely low r ds(on) switch: 0.07 w n no parasitic body diode n built-in short-circuit protection: 2a n built-in thermal overload protection n operates from 2.7v to 5.5v n inrush current limited n ultralow standby current: 0.01 m a n built-in charge pump n controlled rise and fall times: t r = 1ms n single switch in 8-pin so package n dual switch in narrow 16-pin so package charge
pump gate charge
and
discharge
control logic current limit
and thermal
shutdown en v ins v in1 v in2 v in3 v out ltc1477/1478 ?ta01 *** *nmos switches with no parasitic body diodes , ltc and lt are registered trademarks of linear technology corporation. n notebook computer power management n power supply/load protection n supply/battery switch-over circuits n circuit breaker function n "hot swap" board protection n peripheral power protection applicatio n s u switch output voltage output current (a) 0 4.60 output voltage (v) 4.70 4.80 4.90 5.00 5.20 0.25 0.5 0.75 1.00 ltc1477/1478 ?tp02 1.25 1.50 5.10 t a = 25 c
v in1 = v in2 = v in3 = v ins = 5v si plified block diagra m ww
2 ltc1477/LTC1478 supply voltage .......................................................... 7v enable input voltage ...................... (7v) to (gnd C 0.3v) output voltage (off) (note 1) ....... (7v) to (gnd C 0.3v) output short-circuit duration .......................... indefinite junction temperature........................................... 110 c absolute m axi m u m ratings w ww u operating temperature ltc1477c/LTC1478c .............................. 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u symbol parameter conditions min typ max units v in supply voltage range 2.7 5.5 v i vin supply current switch off, enable = 0v l 0.01 10 m a switch on, enable = 5v, v in = 5v l 120 180 m a switch on, enable = 3.3v, v in = 3.3v l 80 120 m a r on on resistance v ins = v in1 = v in2 = v in3 = 5v, i out = 1a 0.07 0.12 w v ins = v in1 = v in2 = v in3 = 3.3v, i out = 1a 0.08 0.12 w v ins = v in1 = 5v, v in2 = v in3 = nc, i out = 0.5a 0.12 0.20 w v ins = v in1 = 3.3v, v in2 = v in3 = nc, i out = 0.5a 0.13 0.20 w i lkg output leakage current off switch off, enable = 0v l 20 m a i sc short-circuit current limit v ins = v in1 = v in2 = v in3 = 5v, v out = 0v, (note 4) 1.60 2.00 2.40 a v ins = v in1 = 5v, v in2 = v in3 = nc, v out = 0v, (note 4) 0.68 0.85 1.02 a v enh enable input high voltage 3.0v v ins 5.5v l 2.0 v v enl enable input low voltage 3.0v v ins 5.5v l 0.8 v i en enable input current 0v v en 5.5v l 1 m a t d+r delay and rise time r out = 100 w , c out = 1 m f, to 90% of final value 0.50 1.00 2.00 ms increase the on resistance of the switch. the LTC1478 gnd pins must be connected together. (see pin functions and block diagram for more detail.) note 3: other channel turned off, i.e. aen and ben = 0v. note 4: the output is protected with fold-back current limit which reduces the short-circuit (0v) currents below peak permissible current levels at higher output voltages. (see typical performance characteristics for further detail on output current versus output voltage). the l denotes specifications which apply over the full operating temperature range. note 1: the v out pins must be connected together. note 2: the v ins and v in1 pins must be connected together. the v in2 and v in3 pins are typically connected to v ins and v in1 pins but can be selectively disconnected to reduce the short-circuit current limit and consult factory for industrial and military grade parts. top view s package
16-lead plastic so 1
2
3
4
5
6
7
8 16
15
14
13
12
11
10
9 av out
av in
av ins
aen
gnd
bv in3
bv in2
bv out
av out
av in2
av in3
gnd
ben
bv ins
bv in1
bv out
t jmax = 110 c, q ja = 100 c/ w electrical characteristics v ins = v in1 = v in2 = v in3 = 5v (note 2), t a = 25 c, unless otherwise noted. each channel of the LTC1478 is tested separately (note 3). t jmax = 110 c, q ja = 120 c/ w 1
2
3
4 8
7
6
5 top view v out
v in2
v in3
gnd v out
v in1
v ins
en s8 package
8-lead plastic so 1477 s8 part marking ltc1477cs8 order part number LTC1478cs order part number
3 ltc1477/LTC1478 typical perfor m a n ce characteristics u w supply current (on) switch resistance switch resistance (5v) supply voltage (v) 0 0 supply current ( a) 50 100 150 200 300 1 234 ltc1477/1478 ?tpc01 56 250 t a = 25 c
output turned on, no load input voltage (v) 1 0 switch resistance ( ) 0.05 0.10 0.15 0.20 0.30 2 345 ltc1477/1478 ?tpc02 67 0.25 t a = 25 c v in2 = v in3 = nc all v in pins
connected junction temperature ( c) 0 0 switch resistance ( ) 0.05 0.10 0.15 0.20 0.25 0.30 25 50 75 100 ltc1477/1478 ?tpc03 125 v ins = v in1 = 5v
v in2 = v in3 = nc all v in pins = 5v switch resistance (3.3v) short-circuit current output current (5v) junction temperature ( c) 0 0 switch resistance ( ) 0.05 0.10 0.15 0.20 0.25 0.30 25 50 75 100 ltc1477/1478 ?tpc04 125 v ins = v in1 = 3.3v
v in2 = v in3 = nc all v in pins = 3.3v output voltage (v) 0 0 output current (a) 1 2 3 4 6 1 234 ltc1477/1478 ?tpc06 56 5 t a = 25 c all v in pins = 5v v in2 = v in3 = nc supply voltage (v) 0 0 short-circuit current (a) 0.5 1.0 1.5 2.0 3.0 1 234 ltc1477/1478 ?tpc05 56 2.5 t j = 25 c all v in pins
connected v in2 = v in3 = nc output current (3.3v) inrush current (5v) inrush current (3.3v) time (ms) ?.4 inrush current (a) output voltage (v)
0 1 2.8 ltc1477/1478 ?tpc09 6 4 0 0.4 1.2 2.0 2 3 2 0 0.8 1.6 2.4 c out = 470 f
r out = 10 c out = 10 f
r out = 10 current
limited t j = 25 c
all v in pins = 3.3v output voltage (v) 0 0 output current (a) 1 2 3 4 6 1 234 ltc1477/1478 ?tpc07 56 5 t a = 25 c all v in pins = 3.3v v in2 = v in3 = nc time (ms) ?.4 inrush current (a) output voltage (v)
0 1 2.8 ltc1477/1478 ?tpc08 6 4 0 0.4 1.2 2.0 2 3 2 0 0.8 1.6 2.4 c out = 470 f
r out = 10 c out = 10 f
r out = 10 current
limited t j = 25 c
all v in pins = 5v
4 ltc1477/LTC1478 ltc1477 en (pin 4): the enable input is a high impedance cmos gate with an esd protection diode to ground and should not be forced below ground. this input has about 100mv of built-in hysteresis to ensure clean switching. v ins , v in1 (pins 3,2): the v ins supply pin must always be connected to the v in1 supply pin (see block diagram). the v ins supply pin provides power for the input control logic, the current limit and thermal shutdown circuitry; plus provides a sense connection to the input power supply. the gate of the nmos switch is powered by a charge pump from the v ins supply pin (see block diagram). the v in1 supply pin provides connection to the drain of 1/2 of the output power device. v in2 , v in3 (pins 7,6): the v in2 and v in3 supply pins are typically tied to the v ins and v in1 supply pins for lowest on resistance; i.e., when all four v in pins are connected together the entire power device is connected (see block diagram). each auxiliary supply pin, v in2 and v in3 , is connected to the drain of 1/4 of the power device. the v in2 and v in3 pins can be selectively disconnected to reduce the short-circuit current limit at the expense of higher r ds(on) . (see applications information section for more details.) v out (pins 1,8): the output pins of the ltc1477 must always be tied together. the output is protected against accidental short circuits to ground by a current limit circuit which protects the system power supply and load against damage. a second level of protection is provided by thermal shutdown circuitry which limits the die tempera- ture to 130 c. LTC1478 aen, ben (pins 4,12): the enable inputs are high imped- ance cmos gates with esd protection diodes to ground and should not be forced below ground. these inputs have about 100mv of built-in hysteresis to ensure clean switching. av ins , av in1 , bv ins , bv in1 (pins 3,2; 11,10): the av ins or bv ins supply pin must always be connected to the av in1 or bv in1 supply pin (see block diagram). the av ins and bv ins supply pins provide power for the input control logic, the current limit and thermal shutdown circuitry; plus, provides a sense connection to the input power supply. the gate of the nmos switch is powered by a charge pump from the av ins and bv ins supply pins (see block diagram). the av in1 and bv in1 supply pins provide connection to the drain of 1/2 of the output power device. av in2 , av in3 , bv in2 , bv in3 , (pins 15,14; 7,6): the av in2 , av in3 , bv in2 and bv in3 supply pins are typically tied to the av ins , av in1 , bv ins and bv in1 supply pins for lowest on resistance; i.e., when all four av in , bv in pins are con- nected together the entire power device is connected (see block diagram). each auxiliary supply pin, av in2 , av in3 , bv in2 and bv in3 , is connected to the drain of approxi- mately 1/4 of the corresponding power device. the av in2 , av in3 , bv in2 and bv in3 pins can be selectively discon- nected to reduce the short-circuit current limit at the expense of higher r ds(on) . (see applications information section for more details.) av out , bv out (pins 1,16; 8,9): the outputs of the LTC1478 are protected against accidental short circuits to ground by a current limit circuit which protects the system power supplies and loads against damage. a second level of protection is provided by thermal shutdown circuitry which limits the die temperature to approximately 130 c. pi n fu n ctio n s uuu
5 ltc1477/LTC1478 operatio n u (ltc1477 or single channel of LTC1478) input ttl-cmos converter the ltc1477 enable input is designed to accommodate a wide range of 3v and 5v logic families. the input threshold voltage is approximately 1.4v with 100mv of hysteresis. the input enables the bias generator, the gate charge pump and the protection circuitry. therefore, when the enable input is turned off, the entire circuit is powered down and the supply current drops below 1 m a. ramped switch control the ltc1477 gate charge pump includes circuitry which ramps the nmos switch on slowly (1ms typical rise time) but turns it off much more quickly (typically 20 m s). bias, oscillator and gate charge pump when the switch is enabled, a bias current generator and high frequency oscillator are turned on. the on-chip capacitive charge pump generates approximately 12v of gate drive for the internal low r ds(on) nmos switch from the power supply. no external 12v supply is required to switch the output. switch protection two levels of protection are designed into the power switch in the ltc1477. the switch is protected against accidental short circuits with a current limit circuit which limits the output current to typically 2a when the output is shorted to ground. the ltc1477 also has thermal shut- down set at approximately 130 c which limits the power dissipation to safe levels. LTC1478 operation the LTC1478 dual protected switch can be thought of as two independent ltc1477 single protected switches. the input supply voltages may be from separate power sources. the ground connection, however, is common to both channels and must be connected to the same potential. (ltc1477 or single channel of LTC1478) block diagra m w applicatio n s i n for m atio n wu u u table 1. effects of disconnecting v in2 and v in3 all v in pins v in3 v in2 and v in3 connected disconnected disconnected r ds(on) 0.07 w 0.09 w 0.12 w i limit 2a 1.5a 0.85a note: 5v operation note that there is an inverse relationship between output current limit and switch resistance. this allows the tailor- ttl-to-cmos
converter oscillator
and bias charge
pump gate charge
and
discharge
control logic current limit
and thermal
shutdown en v ins v in1 v in2 v in3 v out ltc1477/1478 ?bd01 tailoring i limit and r ds(on) for load requirements the ltc1477 is designed to current limit at approximately 2a during a short circuit with all the v in pins connected to the input power supply. it is possible however, to reduce this current by selectively disconnecting two of the four power supply pins (v in2 and v in3 ). table 1 lists the effects of disconnecting these pins on r ds(on) and short-circuit current limit
6 ltc1477/LTC1478 applicatio n s i n for m atio n wu u u ing of the switch parameters to the expected load current and system current limit requirements. a couple of examples are helpful: 1. if a nominal load of 1a was controlled by the switch configured to current limit at 2a (all v in pins connected together), the r ds(on) would be 0.07 w and the voltage drop across the switch would be 70mv. the power dissipated by the switch would only be 70mw. 2. if a nominal load of 0.5a was controlled by the switch configured to current limit at 0.85a (v in2 and v in3 disconnected), the r ds(on) would increase to 0.14 w . but the voltage drop would remain at 70mv and the switch power dissipation would drop to 35mw. supply bypassing for best results, bypass the supply input pins with a single 1.0 m f capacitor as close as possible to the ltc1477. sometimes, much larger capacitors are already available at the output of the power supply. in this case, it is still good practice to use a 0.1 m f capacitor as close as possible to the ltc1477, especially if the power supply output capacitor is more than 2 inches away on the printed circuit board. output capacitor the output pin is designed to ramp on slowly, typically 1ms rise time. therefore, very large output capacitors can be driven without producing voltage spikes on the supply pins (see graphs in typical performance characteristics). the output pin should have a 1 m f capacitor for noise reduction and smoothing. supply and input sequencing the ltc1477 is designed to operate with continuous power (quiescent current drops to < 1 m a when disabled). if the power must be turned off, for example to enter a system sleep mode, the enable input must be turned off 100 m s before the input supply is turned off to ensure that the gate of the nmos switch is completely discharged before power is removed. however, the input control and power can be applied simultaneously during power up. typical applicatio n s u 0.85a protected switch 2a protected switch driving a large capacitive load + c load
100 f 0.1 f ltc1477/1478 ?ta06 on/off 2.7v to 5.5v ltc1477 v out v in2 v in3 gnd v out v in1 v ins en v out + 1 f 0.1 f ltc1477/1478 ?ta05 on/off 2.7v to 5.5v i sc = 0.85a nc nc ltc1477 v out v in2 v in3 gnd v out v in1 v ins en + 1 f 0.1 f ltc1477/1478 ?ta04 on/off 2.7v to 5.5v i sc = 1.5a nc ltc1477 v out v in2 v in3 gnd v out v in1 v ins en 2a protected switch 1.5a protected switch + 1 f 0.1 f ltc1477/1478 ?ta03 on/off 2.7v to 5.5v i sc = 2a v out v in2 v in3 gnd v out v in1 v ins en ltc1477
7 ltc1477/LTC1478 typical applicatio n s u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. adding short-circuit protection to an lt1301 step-up switching regulator (0.01 m a standby current) + ltc1477/1478 ?ta09 lt1304cs8-5 22 m h
sumida
cd54-220 mbrs130lt3 (5v) (2.7v to 4.2v) sw sense nc 220k *primary li-ion battery protection must be provided by an independent circuit lbo v in i lim lbi 34 100 m f
10v
tant 8 2 5 6 7 1 shdn ltc1477 v out v in2 gnd v out v in1 v ins nc nc v in3 en 562k
1% 432k
1% single
li-ion
cell* + 100 m f
16v + 1 m f 5v single li-ion cell to 5v converter/switch with load disconnect below 2.7v + 100 f
10v 0.1 f dn117 ?f03 on/off ltc1477 v out v in2 v in3 gnd v out v in1 v ins en 5v + nc 47 f
16v
tant 0.1 f
12v l1*
10 h
d1
mbrs130lt3 1 8 7 6 3 24 5 sw gnd v in sel shdn sense i lim pgnd lt1301 *coilcraft do1608-103 5v to 3.3v selector switch with slope control and 0.01 m a standby current *allow at least 100ms between 5v and 3.3v switching for discharge of 100 f output capacitor LTC1478 av out bv out bv in2 bv in3 gnd aen av ins av in1 av out bv out bv in1 bv ins ben gnd av in3 av in2 0.1 f 0.1 f 5v 3.3v 3.3v on/off* 5v on/off* + 100 f
10v 1k 5v/2a or
3.3v/2a ltc1477/1478 ?ta08
8 ltc1477/LTC1478 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0995 10k ? printed in usa ? linear technology corporation 1995 related parts part number description comments ltc1153 electronic circuit breaker mosfet driver with adjustable reset time ltc1154 single high side driver mosfet driver with switch status output ltc1155 dual high side driver dual mosfet driver with protection ltc1470 5v and 3.3v v cc switch safeslot tm protected switch in 8-lead so ltc1471 dual 5v and 3.3v v cc switch dual version of ltc1470 in 16-lead so ltc1472 pcmcia v cc and vpp switches complete single channel safeslot protection safeslot is a trademark of linear technology corporation. dimension in inches (millimeters) unless otherwise noted. package descriptio n u 0.016 ?0.050
0.406 ?1.270 0.010 ?0.020
(0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010
(0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157**
(3.810 ?3.988) 16 15 14 13 0.386 ?0.394*
(9.804 ?10.008) 0.228 ?0.244
(5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069
(1.346 ?1.752) 0.014 ?0.019
(0.355 ?0.483) 0.004 ?0.010
(0.101 ?0.254) 0.050
(1.270)
typ dimension does not include mold flash. mold flash
shall not exceed 0.006" (0.152mm) per side
dimension does not include interlead flash. interlead
flash shall not exceed 0.010" (0.254mm) per side
*
** s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050
0.406 ?1.270 0.010 ?0.020
(0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010
(0.203 ?0.254) so8 0695 0.053 ?0.069
(1.346 ?1.752) 0.014 ?0.019
(0.355 ?0.483) 0.004 ?0.010
(0.101 ?0.254) 0.050
(1.270)
bsc 1 2 3 4 0.150 ?0.157**
(3.810 ?3.988) 8 7 6 5 0.189 ?0.197*
(4.801 ?5.004) 0.228 ?0.244
(5.791 ?6.197) dimension does not include mold flash. mold flash
shall not exceed 0.006" (0.152mm) per side
dimension does not include interlead flash. interlead
flash shall not exceed 0.010" (0.254mm) per side
*
** s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610)
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